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IBM 308X

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IBM 308X
IBM 3081
ManufacturerInternational Business Machines Corporation (IBM)
Product familyIBM 3081
IBM 3083
IBM 3084
Release date1980 for the 3081; 1982 for the 3083 & 3084
DiscontinuedAugust 4, 1987 (all 308X)

The IBM 308X is a line of mainframe computers, of which the first model, the Model 3081 Processor Complex, was introduced November 12, 1980.[1][NB 1] It consisted of a 3081 Processor Unit with supporting units.

Later models in the series were the 3083[2] and the 3084.[3] The 3083 was announced March 31 and the 3084 on September 3, both in 1982.

The IBM 308X line introduced the System/370 Extended Architecture[4] (S/370-XA) required by the new MVS/SP V2[5] and the Start Interpretive Execution[6] (SIE) instruction used by the new Virtual Machine/eXtended Architecture Migration Aid[7] (VM/XA MA).

All three 308X systems, which IBM had marketed as "System/370-Compatibles,"[8] were withdrawn August 4, 1987.

IBM 3081

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The initial 3081 offered, the 3081D, was a 5 MIPS machine. The next offering, the 3081K, was a 7 MIPS machine. Last came the 3081G, again a 5 MIPS machine.

The 3081D was announced Nov 12, 1980; the 3081K came nearly a year later; the 3081G was introduced September 3, 1982 as part of the initial 3084 announcement.[3] The 3081G was replacing the 3081D models.

"The IBM 3081 Processor Complex offers flexible growth steps in the 308X family of processors, between the 3083 Model Groups C, E, B and J over 3081G and 3081K to the 3084."[9]

The 3081 was "two processors in a single box ... it was not possible to partition it and run it as two independent machines."[10]

The dyadic concept offers "under the cover" dual processors.

All models of 3081 and 3083 had the same size, components and footprint; the CPU itself (3081 or 3083), the service processor that also contained the channels (3082), and the water pump/coolant unit (3087).

The 308X Processor Complex was using 400 Hz power, this could be supplied by either an optional motor/generator unit (3089), or it could be supplied by an external power source.

3081 as successor to 3033

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Some key technological features of the 3081, compared to the previous most powerful processor, the 3033, were the following:

  • About 800,000 circuits implemented in large scale integration, using up to 704 logic circuits per chip, which provided the required performance, reliability, and serviceability that were design goals
  • "Elimination of one complete level of packaging, the card level"[11]: 2 
  • Water cooling, which provides heat removal from chips beyond the ability of conventional air cooling
  • A machine cycle time of 26 nanoseconds (38 MHz equivalent CPU)
  • Reduced power consumption, 23 kilowatts for a 3081-D16 versus 68 kilowatts for a 3033-U16
  • Approximately double the instruction-execution rate of the 3033
  • Two central processor components[11]: pages 2, 3, 8 

Both central processors have access to channels (as many as 24), and main memory (up to 32 megabytes[NB 2]).[11]: pages 3, 4 

The elimination of a layer of packaging was achieved through the development of the Thermal Conduction Module (TCM), a flat ceramic module containing about 30,000 logic circuits on up to 118 chips. The TTL chips (which were not compatible with the TTL chips sold on the open market by many manufacturers) were joined face-down (sometimes called "flip chip") to the TCM with an array of 11 × 11 solder pads. The TCM contains 33 metalized layers which distribute signals and power. "A module is connected to the next level of packaging through 1800 pins (1200 are available for signals, 500 pins are available for power, and 100 pins are spare)." (p. 7) The module is fitted with a helium-filled metal cap, which contains one piston per chip; the piston presses against the back of each chip to provide a heat conduction path from the chip to the cap. A water-cooled cold plate is attached to the cap; the water temperature is approximately 24 °C. This arrangement provides cooling of the module heat flux on the order of 105 watts per square meter, which is about a tenfold increase over the 3033 processor.[11]: pp.4–8 

The internal code name of the 3081 was Adirondack.[12]

IBM 3083

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The IBM 3083 was described by an IBMer as "never intended to be built,"[10] adding that the 308X was to only be the 3081 and 3084, and that the 3083 was aimed at "the ACP/TPF market" which wanted a "fast... uniprocessor."[10]

Of the various 3083 models listed by IBM in their announcement, the CX has the slowest instruction execution rate.[2]
Next in speed are the E and EX, followed by B and BX. The J and JX are the fastest 3083s.

IBM's information sheet says:

  • The 3083 Model CX has an instruction execution rate of about 0.75 times that of a 3083 Model EX.
  • The 3083 Models B and BX have an instruction execution rate ranging from 1.4 to 1.5 times the 3083 Models E and EX, respectively.
  • The 3083 Models J and JX have an instruction execution rate ranging from 1.8 to 2.0 times the 3083 Models E and EX, respectively.

Collectively, the fastest is 2.667 times the performance of the slowest.[NB 3]

IBM 3084

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Announced September 3, 1982 and withdrawn August 4, 1987.[3] It could be configured with 32, 48 or 64 million bytes of main memory. Later on the 3084X could have up to 128 MB of storage. The 3084 was a 14 MIPS machine.

"The 3084 was two 3081 tied together to make a 4-way SMP."[3][10] ("that can operate .. as two independent" dual-processors)([NB 4]

While all 3081/3083 shared the same physical footprint, the 3084 system doubled this setup, the CPU was double in length, two 3082, and two 3087 was used. For systems using the optional 3089, two units were required.

The 3084 could run in two different modes. When running in PP-mode (Partial Processing), it was configured as two independent systems. The other mode was called SI-mode (Single Image), then all four processors were running as one system.

See also

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Notes

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  1. ^ IBM used a capital X when referring to 308X, as did others needing an official reference; see the Congressional Record reference.
  2. ^ 32×220 bytes
  3. ^ range of relative performance = 2.0 / 0.75
  4. ^ 3081 + 3081 with same serial number, but two on/off switches. In IBM's words: "four central processing units that can operate as a tightly coupled multiprocessor or as two independent "dyadic" configurations" - IBM didn't announce it as a Quad, just two Dyadics (twins)."

References

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  1. ^ "3081 Processor Complex". IBM Archives. IBM. 23 January 2003. Archived from the original on December 26, 2004.
  2. ^ a b "3083 Processor Complex". IBM Archives. IBM. 23 January 2003. Archived from the original on March 11, 2005.
  3. ^ a b c d "3084 Processor Complex". IBM Archives. IBM. 23 January 2003. Archived from the original on December 15, 2004.
  4. ^ IBM System/370 Extended Architecture Principles of Operation (PDF) (Second ed.). IBM. January 1987. SA22-7085-1. Retrieved October 27, 2022.
  5. ^ "IBM Large Systems Announcement Overview". IBM (Announcement letter). October 21, 1981. LTR ENUS283-042. Archived from the original on 2023-06-02. Retrieved November 17, 2022.
  6. ^ IBM System/370 Extended Architecture Interpretive Execution (PDF) (First ed.). IBM. January 1984. SA22-7095-0. Retrieved October 27, 2022.
  7. ^ "Virtual Machine/eXtended Architecture Migration Aid". IBM (Announcement letter). October 21, 1981. ZP81-0811. Retrieved October 27, 2022.
  8. ^ "IBM Archives: System/370-Compatibles Dates and characteristics". 23 January 2003. Archived from the original on January 16, 2005.
  9. ^ IBM (1982). "3081 Processor Complex". IBM (marketing brochure). Archived from the original on December 26, 2004. Retrieved September 18, 2008.
  10. ^ a b c d Anne & Lynn Wheeler. "IBM 9020 computers used by FAA (was Re: EPO stories (was: HELP IT'S HOT!!!!!))". Newsgroup: alt.folklore.computers.
  11. ^ a b c d Pittler, M. S.; Powers, D. M.; Schnabel, D. L. (1982). "System Development and Technology Aspects of the IBM 3081 Processor Complex". IBM Journal of Research and Development. 26 (1): 2–11. doi:10.1147/rd.261.0002.
  12. ^ "Congressional Record". FAS. July 12, 1989. p. H3666. Retrieved September 18, 2008.

Further reading

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Photos

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